Methods and apparatus for timed hardware delay for reductions in instruction fetch traffic

Abstract

An apparatus and method for timed hardware delay for reducing instruction fetch traffic. For example, an example processor comprises: memory controller to couple to a system memory; a plurality of cores coupled to the memory controller; a shared cache coupled to the plurality of cores, the shared cache to store a plurality of cache lines; an instruction steam buffer (ISB) to store cache lines of the plurality of cache lines containing instructions; an instruction cache to be filled with the instructions, or a subset thereof; and branch prediction circuitry to mark each cache line in the ISB as speculative or non-speculative, the branch prediction circuitry to delay flushing of a first cache line marked as speculative to the shared cache by an expected time for a subsequent cache line added to the ISB to trigger a clear signal, causing the first cache line to be flushed to the shared cache.