The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jun. 26, 2023
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventor:

Zhou Yao, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/3115 (2006.01); H01L 21/3213 (2006.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/31155 (2013.01); H01L 21/32133 (2013.01); H10D 64/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/038 (2025.01); H10D 64/667 (2025.01);
Abstract

The present application discloses a method for manufacturing a metal gate, comprising: step, providing a semiconductor substrate on which dummy polysilicon gates are formed, wherein a first gate dielectric layer is formed at the bottom of the dummy polysilicon gates, and a spacing region between the dummy polysilicon gates is filled with a zero interlayer dielectric; step, removing the dummy polysilicon gates, comprising: step, performing first dry etching to remove a part of the thickness of the dummy polysilicon gate; step, performing carbon ion implantation to form a carbon containing surface region of the zero interlayer dielectric; and step, performing second wet etching to fully remove the remaining dummy polysilicon gates; step, performing third etching to remove the first gate dielectric layer; and step, forming a second gate dielectric layer and a metal gate.


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