The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Dec. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yu-Lien Huang, Jhubei, TW;

Ching-Feng Fu, Taichung, TW;

Guan-Ren Wang, Hsinchu, TW;

Che-Ming Hsu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01);
Abstract

A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.


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