The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jun. 08, 2022
Applicant:

Trinno Technology Co., Ltd., Seoul, KR;

Inventors:

Kwang Hoon Oh, Seoul, KR;

Junyoung Choi, Seoul, KR;

Jin Young Jung, Seoul, KR;

Soo Seong Kim, Seoul, KR;

Chongman Yun, Seoul, KR;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 12/00 (2025.01); H03K 17/567 (2006.01); H10D 62/10 (2025.01); H10D 89/00 (2025.01);
U.S. Cl.
CPC ...
H10D 12/481 (2025.01); H03K 17/567 (2013.01); H10D 62/127 (2025.01); H10D 89/215 (2025.01);
Abstract

Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.


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