The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jan. 04, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Li-Zhen Yu, New Taipei, TW;

Huan-Chieh Su, Tianzhong Township, TW;

Lin-Yu Huang, Hsinchu, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); B82Y 10/00 (2011.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76224 (2013.01); H01L 21/76898 (2013.01); H10D 84/83 (2025.01);
Abstract

Methods of forming through vias for providing connections between a front-side of a substrate and a backside of the substrate and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure on a substrate; a first isolation feature extending partially through the gate structure; a first conductive feature extending through the first isolation feature; and a second conductive feature extending partially through the gate structure, the second conductive feature being electrically coupled to the first conductive feature.


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