The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2025
Filed:
Dec. 22, 2022
Applicant:
Intel Ndtm Us Llc, Santa Clara, CA (US);
Inventors:
Assignee:
Intel NDTM US LLC, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10B 41/20 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10B 41/20 (2023.02); H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02);
Abstract
A semiconductor circuit includes multiple decks of semiconductor devices, each deck having multiple three-dimensional (3D) stacks. The semiconductor circuit has a nitride layer between the first deck and the second deck. The nitride layer has a self-aligned pillar through the nitride layer to electrically connect the first deck to the second deck. The nitride layer can have multiple sublayers, with a mirrored gradient doping, with lower doping toward the middle of the nitride layer and higher doping toward the outsides of the nitride layer that interfaces with the decks.