The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jan. 17, 2022
Applicants:

Hua Hong Semiconductor (Wuxi) Limited, Wuxi, CN;

Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, CN;

Inventors:

Jialong Li, Wuxi, CN;

Peng Huang, Wuxi, CN;

Xiao Fan, Wuxi, CN;

Wensheng Qian, Wuxi, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/76202 (2013.01); H10F 39/014 (2025.01); H10F 39/807 (2025.01);
Abstract

A method for making a deep trench isolation of a CIS device includes: growing a first epitaxial layer on a substrate; forming a hard mask layer on the first epitaxial layer; performing photolithography and etching processes to form deep trenches arranged longitudinally and transversely in the first epitaxial layer; forming a second epitaxial layer in the deep trenches; performing a thermal oxidation process to form a first oxide layer on the surface of the second epitaxial layer; completely filling the deep trenches with polysilicon; performing a back-etching process to expose sidewalls of the first oxide layer in the deep trenches; forming a second oxide layer on the top of the polysilicon; removing the hard mask layer and the first oxide layer above the second oxide layer; rapidly growing a third epitaxial layer; and performing a CMP process to form a deep trench isolation on the substrate.


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