Memory device and read method adjusting multiple bit line voltages for error mitigation reading

Abstract

A memory device and a read method therefor are disclosed. The memory device includes first to third memory cell strings. The memory device is a three-dimensional NAND flash memory with high capacity and high performance. Each of the memory cell strings includes first to third memory cells. The read method includes: performing a first read operation of the memory device to the second memory cell in the second memory cell string, the first read operation includes applying a first bit line voltage to a first bit line, a second bit line, and a third bit line; in response to the failure of the first read operation, performing a second read operation of the memory device, the second read operation includes: applying a set of second bit line voltages to the first bit line, the second bit line and the third bit line.