The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Mar. 13, 2024
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Ranjith Kumar Sajja, Santa Clara, CA (US);

Sreekanth Godey, Santa Clara, CA (US);

Anirudh R. Acharya, Santa Clara, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/12 (2006.01); G06F 9/50 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 9/505 (2013.01); G06F 11/3409 (2013.01);
Abstract

Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.


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