The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Oct. 08, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Huan-Chieh Su, Tianzhong Township, TW;

Chih-Hao Wang, Baoshan Township, TW;

Kuo-Cheng Ching, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/66 (2025.01); H01L 21/02 (2006.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/671 (2025.01); H01L 21/02532 (2013.01); H01L 21/0262 (2013.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/691 (2025.01); H10D 84/0135 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01);
Abstract

The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.


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