The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jul. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

I-Wen Huang, Taipei, TW;

Ching-Feng Fu, Taichung, TW;

Guan-Ren Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 64/258 (2025.01); H01L 21/28518 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01);
Abstract

A semiconductor device and a method are provided. The semiconductor device includes gate structures extending on a substrate along a first direction and arranged in a second direction in parallel with one another, source and drain regions disposed in the substrate between the parallel gate structures, and dielectric structures disposed on the substrate and between the gate structures. The semiconductor device further includes an ILD layer disposed over the gate structures and the dielectric structures, contact structures disposed beside and between the parallel gate structures and separators embedded in the ILD layer. Each contact structure extends vertically through the ILD layer and the dielectric structures, and the separators are disposed above the gate structures and disposed beside the contact structures. Each contact structure extends along the first direction and extends between two adjacent separators, and each separator extending in the second direction overlaps at least two adjacent gate structures.


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