The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Dec. 21, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hokyun An, Seoul, KR;

Bumsoo Kim, Hwaseong-si, KR;

Hyunseung Kim, Bucheon-si, KR;

Guangfan Jiao, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H01L 21/28 (2006.01); H01L 21/3115 (2006.01); H10D 30/60 (2025.01); H10D 64/27 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 64/118 (2025.01); H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 21/3115 (2013.01); H10D 30/60 (2025.01); H10D 64/513 (2025.01); H10D 64/667 (2025.01); H10D 64/685 (2025.01); H10D 64/691 (2025.01); H10D 84/0177 (2025.01); H10D 84/0181 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.


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