The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jun. 05, 2024
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Takuji Maekawa, Kyoto, JP;

Mitsuru Morimoto, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/832 (2025.01); H01L 21/02 (2006.01); H10D 8/60 (2025.01); H10D 12/00 (2025.01); H10D 30/66 (2025.01); H10D 62/40 (2025.01);
U.S. Cl.
CPC ...
H10D 62/8325 (2025.01); H01L 21/02378 (2013.01); H01L 21/02433 (2013.01); H01L 21/02516 (2013.01); H01L 21/02529 (2013.01); H01L 21/02595 (2013.01); H10D 62/405 (2025.01); H10D 8/60 (2025.01); H10D 12/441 (2025.01); H10D 30/66 (2025.01); H10D 30/668 (2025.01);
Abstract

A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer () is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.


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