The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Dec. 11, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Pei-Yu Wang, Hsinchu, TW;

Sai-Hooi Yeong, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01);
U.S. Cl.
CPC ...
H10D 30/797 (2025.01); H01L 21/02488 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02535 (2013.01); H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/6211 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/792 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01);
Abstract

A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.


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