The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jul. 28, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Lung Tung, Kaohsiung, TW;

Xiaodong Wang, Hsinchu, TW;

Jhon Jhy Liaw, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01);
Abstract

An exemplary method includes receiving a device layout for a standard cell that includes a transistor and a multilayer interconnect. The multilayer interconnect includes a power line, signal lines, a source contact connected to the power line and a source of the transistor, and a drain contact connected to one of the signal lines and a drain of the transistor. The method includes modifying the device layout for the standard cell. For example, if performance of the standard cell is sensitive to power-related features, the method includes enlarging the power line and the source contact and shrinking the signal lines and the drain contact. If performance of the standard cell is sensitive to signal-related features, the method includes shrinking the power line and the source contact and enlarging the signal lines and the drain contact. A cell height of the standard cell is the same after modifying the device layout.


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