The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Apr. 08, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Darshan Gandhi, Palo Alto, CA (US);

Manish K. Shah, Austin, TX (US);

Raghu Prabhakar, San Jose, CA (US);

Gregory Frederick Grohoski, Bee Cave, TX (US);

Youngmoon Choi, Milpitas, CA (US);

Jinuk Shin, San Jose, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/30 (2006.01); G01R 31/27 (2006.01); G06F 1/08 (2006.01); G06F 1/28 (2006.01); G06F 1/324 (2019.01); G06F 1/3206 (2019.01);
U.S. Cl.
CPC ...
G06F 1/305 (2013.01); G01R 31/275 (2013.01); G06F 1/08 (2013.01); G06F 1/28 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01);
Abstract

An integrated circuit (IC) includes an array of compute units. Each compute unit is configured such that, when transitioning from not processing data to processing data, the compute unit makes an individual contribution to an aggregate time rate of change of current drawn by the IC. Control circuitry is configurable to, for each compute unit of the array of compute units, control when the compute unit is eligible to transition from not processing data to processing data relative to when the other compute units start processing data to mitigate supply voltage droop caused by the aggregate time rate of change of current drawn by the IC through inductive loads of the IC.


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