The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jun. 06, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Harish Kumar, Noida, IN;

Nitin Kumar, Greater Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318544 (2013.01); G01R 31/318555 (2013.01); G01R 31/318558 (2013.01); G01R 31/318563 (2013.01); G01R 31/318586 (2013.01);
Abstract

A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.


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