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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12493072 B1

PDFFull Text
Date of Patent:
Dec. 09, 2025

Filed:

Dec. 14, 2020

System and method for identifying design faults or semiconductor modeling errors by analyzing failed transient simulation of an integrated circuit

Applicant:

Bayes Electronics Technology Co., Ltd, Zhejiang, CN;

Inventor:

Gang Peter Fang, Zhejiang, CN;

Assignee:

Bayes Electronics Technology Co., Ltd, Shaoxing, CN;

Attorneys:

MUNCK WILSON MANDALA L.L.P

GREGORY MICHAEL HOWISON

EDWARD JORGENSON

BRIAN WALKER

JOHN J ARNOTT

WILLIAM HOWISON

KEITH D HARDEN

Primary Examiner:

Bijan Mapar

Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 27/28 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2848 (2013.01); G01R 27/28 (2013.01); G01R 31/2812 (2013.01); G01R 31/31705 (2013.01);
Abstract

A method for detecting non-convergence error in a transient circuit simulation wherein a circuit netlist and control statements associated with a circuit for the transient circuit simulation are received. A transient circuit simulation is performed responsive to a time point. Whether a non-convergence error has occurred during transient circuit simulation is determined. A transient debug mode is actuated responsive to determination of occurrence of the non-convergence error. The steps of performing the transient circuit simulation and determining whether a non-convergence error has occurred are repeated after actuation of the transient debug mode. Results of the transient circuit simulation are provided responsive to a determination of non-occurrence of a non-convergence error.

Find Patent Forward Citations

Fang, Gang. (2025). System and method for identifying design faults or semiconductor modeling errors by analyzing failed transient simulation of an integrated circuit (U.S. Patent No. 12493072). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12493072

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