The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Oct. 09, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Vladimir Odnoblyudov, Eagle, ID (US);

Martin F. Schubert, Mountain View, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01R 31/26 (2020.01); H10H 20/01 (2025.01); H10H 20/812 (2025.01); H10H 20/813 (2025.01); H10H 20/825 (2025.01); H10H 20/851 (2025.01); H10H 20/855 (2025.01); H10H 20/857 (2025.01); H10H 20/831 (2025.01); H10H 20/84 (2025.01); H10H 20/858 (2025.01);
U.S. Cl.
CPC ...
H10H 20/857 (2025.01); H10H 20/01335 (2025.01); H10H 20/018 (2025.01); H10H 20/812 (2025.01); H10H 20/813 (2025.01); H10H 20/825 (2025.01); H10H 20/8511 (2025.01); H10H 20/8513 (2025.01); H10H 20/855 (2025.01); H01L 2924/0002 (2013.01); H10H 20/036 (2025.01); H10H 20/0361 (2025.01); H10H 20/0363 (2025.01); H10H 20/0364 (2025.01); H10H 20/8312 (2025.01); H10H 20/8316 (2025.01); H10H 20/84 (2025.01); H10H 20/8585 (2025.01);
Abstract

Vertical solid-state transducers ('SSTs') having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.


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