The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Sep. 28, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byounghak Hong, Albany, NY (US);

Gunho Jo, Clifton Park, NY (US);

Sooyoung Park, Clifton Park, NY (US);

Hyoeun Park, Cohoes, NY (US);

Wookhyun Kwon, Hwaseong-si, KR;

Jaehong Lee, Albany, NY (US);

Kang-Ill Seo, Albany, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/60 (2025.01); H10D 8/00 (2025.01); H10D 10/60 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 84/619 (2025.01); H10D 8/422 (2025.01); H10D 10/60 (2025.01); H10D 62/121 (2025.01);
Abstract

Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.


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