The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Sep. 16, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sagarika Mukesh, Albany, NY (US);

Tao Li, Slingerlands, NY (US);

Prabudhya Roy Chowdhury, Albany, NY (US);

Liqiao Qin, Albany, NY (US);

Nikhil Jain, Apple Valley, MN (US);

Ruilong Xie, Niskayuna, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 23/48 (2006.01); H10D 62/13 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H01L 23/481 (2013.01); H10D 62/151 (2025.01); H10D 84/834 (2025.01);
Abstract

A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.


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