The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jan. 20, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Chi Dong Nguyen, Munich, DE;

Till Schlösser, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H10D 62/116 (2025.01); H10D 30/65 (2025.01); H10D 62/393 (2025.01); H10D 64/117 (2025.01);
Abstract

A field effect transistor, FET, is proposed. The FET includes a source region of a first conductivity type that is electrically connected to a source electrode at a first surface of a semiconductor body. The FET further includes a drain region of the first conductivity type that is electrically connected to a drain electrode at the first surface. A dielectric structure is arranged between the source region and the drain region along a first lateral direction. The dielectric structure includes a gate dielectric on the first surface and a field dielectric structure having a bottom side below the first surface. The FET further includes a gate electrode on the gate dielectric. The gate electrode and the field dielectric structure are spaced from each other along the first lateral direction. The FET further includes a field electrode having a bottom side below a top side of the field dielectric structure.


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