The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Feb. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ken-Ichi Goto, Hsinchu, TW;

Cheng-Yi Wu, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 62/40 (2025.01); H10D 62/84 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6741 (2025.01); H01L 21/02488 (2013.01); H01L 21/02491 (2013.01); H01L 21/02502 (2013.01); H01L 21/02516 (2013.01); H01L 21/02521 (2013.01); H01L 21/02532 (2013.01); H01L 21/02565 (2013.01); H01L 21/02598 (2013.01); H01L 21/02609 (2013.01); H10D 30/031 (2025.01); H10D 30/6739 (2025.01); H10D 30/675 (2025.01); H10D 30/6755 (2025.01); H10D 62/405 (2025.01); H10D 86/423 (2025.01); H10D 86/425 (2025.01); H10D 86/431 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01); H10D 62/84 (2025.01);
Abstract

A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.


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