The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Apr. 02, 2024
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Cheng-Yu Lin, Hsinchu, TW;
Yung-Chen Chien, Hsinchu, TW;
Jia-Hong Gao, Hsinchu, TW;
Jerry Chang Jui Kao, Hsinchu, TW;
Hui-Zhong Zhuang, Hsinchu, TW;
Assignee:
ASSIER CONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01); H03K 5/134 (2014.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); H03K 3/012 (2013.01); H03K 3/0372 (2013.01); H03K 3/356104 (2013.01); H03K 5/134 (2014.07);
Abstract
An integrated circuit (IC) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. The slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.