The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jan. 05, 2023
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Mingxing Zuo, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/4842 (2013.01); H01L 21/4853 (2013.01); H01L 23/49541 (2013.01); H01L 23/49811 (2013.01); H01L 23/5386 (2013.01); H01L 24/05 (2013.01); H01L 24/43 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 25/50 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/43 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45139 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48229 (2013.01); H01L 2224/85444 (2013.01); H01L 2224/85447 (2013.01); H01L 2224/85455 (2013.01);
Abstract

Embodiments relate to the field of semiconductors, and provide a package structure and a method for fabricating the same. The package structure includes: a stack including a plurality of semiconductor devices stacked; a plurality of electrical connection portions positioned on a same side of the stack, each of the electrical connection portions being electrically connected to a corresponding semiconductor device, wherein in a direction distant from the stack, heights of different electrical connection portions gradually increase; and a plurality of wires electrically connected to each of the electrical connection portions and a corresponding semiconductor device, wherein the higher a layer where one semiconductor device is positioned in the stack, the farther one electrical connection portion connected to this semiconductor device is away from the stack. At least yield and reliability of the package structure can be improved while satisfying development of miniaturization of the package structure.


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