The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Oct. 19, 2022
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

I-Jye Lin, New Taipei, TW;

Gary K. Yeap, Fremont, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 23/481 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H10D 88/00 (2025.01); H01L 2224/16245 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06596 (2013.01);
Abstract

Techniques for determining a density of through-silicon vias (TSVs) in a three-dimensional (3D) stacked die are disclosed. In some embodiments, such techniques may include obtaining first power consumption information associated with a first die of the 3D stacked die; obtaining second power consumption information associated with a second die of the 3D stacked die; identifying, on the first die, an area associated with the second die, the identified area overlapping an area associated with the first die; and determining a density of TSVs for the identified area based at least on the first power consumption information and the second power consumption information.


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