The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jan. 05, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Makoto Kitagawa, Folsom, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/2255 (2013.01); G11C 11/221 (2013.01); G11C 11/2273 (2013.01);
Abstract

Methods, systems, and devices for mitigating disturbance of digit lines at plate edges are described. Generally, the described techniques relate to disturbance mitigation for one or more memory cells of a sub-array associated with an unselected digit lines located at an edge of the sub-array by including an additional shunt configured to selectively couple the edge digit lines with an associated plate line. For example, a central digit line may be coupled with a respective one of a first set of selection components and a respective one of a second set of selection components, while an edge digit line may be coupled with a respective one of the first set of selection components, a respective one of the second set of selection components, as well as a respective one of a third set of selection components.


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Kitagawa, Makoto. (2025). Mitigating disturbance of digit lines at plate edges (U.S. Patent No. 12488822). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12488822

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