The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2025
Filed:
Jul. 20, 2023
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Jyun-Hong Shih, Hsinchu, TW;
Min-Cheng Chen, Hsinchu County, TW;
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Abstract
A ferroelectric memory structure including a substrate, first and second conductive lines, first and second dielectric layers, a channel pillar, a gate pillar, and a ferroelectric material layer is provided. The first conductive line is located on the substrate. The first dielectric layer is located on the first conductive line. The channel pillar is located on the first conductive line and in the first dielectric layer. The second conductive line is located on the first dielectric layer and the channel pillar. The gate pillar passes through the second conductive line and is located in the channel pillar. The second dielectric layer is located between the gate pillar and the first conductive line, between the gate pillar and the channel pillar, and between the gate pillar and the second conductive line. The ferroelectric material layer is located between the gate pillar and the second dielectric layer.