The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2025
Filed:
Jan. 04, 2024
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Wei Cheng Wu, Zhubei, TW;
Harry-Hak-Lay Chuang, Zhubei, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/30 (2023.01); H01L 21/306 (2006.01); H01L 21/321 (2006.01); H10B 10/00 (2023.01); H10B 41/49 (2023.01); H10B 43/00 (2023.01); H10B 43/30 (2023.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); H01L 21/30604 (2013.01); H01L 21/3212 (2013.01); H10B 41/49 (2023.02); H10B 43/00 (2023.02); H10B 43/30 (2023.02); H10D 64/017 (2025.01); H10D 64/035 (2025.01); H10D 84/0144 (2025.01); H10D 84/038 (2025.01); H10B 10/18 (2023.02);
Abstract
An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.