The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Aug. 29, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ming-Fa Chen, Hsinchu, TW;

Yun-Han Lee, Hsinchu, TW;

Lee-Chung Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/486 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0655 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H01L 23/5385 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/13081 (2013.01);
Abstract

A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.


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