The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Feb. 13, 2023
Applicant:

Globalwafers Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Yuan Hsu, Hsinchu, TW;

Chun-Chin Tu, Zhubei, TW;

Yau-Ching Yang, Hsinchu County, TW;

Shih-Chiang Chen, Hsinchu, TW;

Assignee:

GlobalWafers Co., Ltd., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/304 (2006.01); B24B 37/04 (2012.01); H01L 21/02 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/304 (2013.01); B24B 37/042 (2013.01); H01L 21/02532 (2013.01); H01L 22/20 (2013.01);
Abstract

A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.


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