The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Jan. 09, 2023
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Mayukh Bhattacharya, Palo Alto, CA (US);

Peilin Jiang, SAnta Clara, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 11/00 (2006.01); G06F 11/26 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 11/008 (2013.01); G06F 11/261 (2013.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01);
Abstract

A system and method for inserting test points during circuit design testing are presented. The method includes partitioning a circuit design into a plurality of blocks and determining a first potential defect and a second potential defect for the circuit design. The method also includes simulating the circuit design by injecting, into the circuit design, the first potential defect to produce a first set of outputs of the plurality of blocks and simulating the circuit design by injecting, into the circuit design, the second potential defect to produce a second set of outputs of the plurality of blocks. The method further includes determining a set of output nodes of the plurality of blocks and generating a test that, when executed, measures signals at the set of output nodes.


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