The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Sep. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

John R. Cherukuri, Austin, TX (US);

Roan M. Nicholson, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G01R 19/165 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31727 (2013.01); G01R 19/16576 (2013.01);
Abstract

Embodiments herein relate to an apparatus comprising: a first circuit with a plurality of stages; and a second circuit communicatively coupled with the first circuit, wherein the second circuit includes: a plurality of tap lines, wherein respective tap lines of the plurality of tap lines are coupled between two stages of the plurality of stages; and the logic, wherein the logic is to identify, based on an average voltage measurement of at least one tap line, a status of a duty-cycle of a signal propagating through a stage of the first circuit. Other embodiments may be described and claimed.


Find Patent Forward Citations

Cherukuri, John. (2025). Techniques for identification and correction of clock duty-cycle (U.S. Patent No. 12480992). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12480992

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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