The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Jan. 09, 2024
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Yu-Lin Yang, Hsinchu, TW;

Po-Chao Tsao, Hsinchu, TW;

Yun-San Huang, Hsinchu, TW;

Chia-Chun Sun, Hsinchu, TW;

Chin-Wei Lin, Hsinchu, TW;

Tung-Hsing Lee, Hsinchu, TW;

Chih-Min Lin, Hsinchu, TW;

Chia-Yu Yang, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2879 (2013.01); G01R 31/287 (2013.01); G01R 31/2875 (2013.01); G01R 31/2894 (2013.01);
Abstract

A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature according to the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures according to the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer according to the DVS block target temperature.


Find Patent Forward Citations

Quick Actions:

Yang, Yu-Lin. (2025). Dynamic voltage stress condition optimization method and dynamic voltage stress condition optimization system capable of performing block-based dynamic voltage stress wafer testing process (U.S. Patent No. 12480987). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12480987

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