The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Mar. 04, 2024
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chih-Fan Huang, Kaohsiung, TW;
Hung-Chao Kao, Taipei, TW;
Yuan-Yang Hsiao, Taipei, TW;
Tsung-Chieh Hsiao, Changhua County, TW;
Hsiang-Ku Shen, Hsinchu, TW;
Hui-Chi Chen, Hsinchu County, TW;
Dian-Hau Chen, Hsinchu, TW;
Yen-Ming Chen, Hsin-Chu County, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
The present disclosure is directed to a semiconductor device. The semiconductor device includes a multi-layer interconnect structure disposed over a substrate, a dielectric layer disposed over the multi-layer interconnect structure, and a metal-insulator-metal (MIM) capacitor disposed over the dielectric layer. The MIM capacitor includes a bottom electrode disposed on a top surface of the dielectric layer, a top electrode disposed above the bottom electrode, and an insulating layer interposed between the bottom electrode and the top electrode. The bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer. The top electrode has a vertical sidewall with respect to the top surface of the dielectric layer. The insulating layer covers the slanted sidewall of the bottom electrode.