The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Apr. 10, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Massimo Pozzoni, Pavia, IT;

Paolo Viola, Pavia, IT;

Pasquale D'Argenio, Mercogliano, IT;

Augusto Andrea Rossi, Pavia, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01); H03K 5/24 (2006.01); H03K 17/567 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); H03K 5/24 (2013.01); H03K 17/567 (2013.01);
Abstract

In embodiments, a clock signal calibration circuit for communication transmitters includes a multiplexer that creates a combined output pattern from input data patterns in reaction to the clock signal's edges. It uses a calibration data pattern generator, which supplies two sequential patterns—the second being a shifted copy of the first—to the multiplexer. An averaging circuit then generates two averaged signals corresponding to these patterns. Duty cycle control circuitry corrects clock signal imbalances if these averaged signals are unequal, thus adjusting the duty cycle distortion to achieve an ideal 50% duty cycle.


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