The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Sep. 19, 2022
Applicant:
Magnachip Semiconductor, Ltd., Cheongju-si, KR;
Inventors:
Assignee:
Magnachip Semiconductor, Ltd., Cheongju-si, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 24/29 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/05005 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05576 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/05691 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13019 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/29007 (2013.01); H01L 2224/29019 (2013.01); H01L 2224/29083 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/29155 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/30101 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/35121 (2013.01);
Abstract
A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.