The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Oct. 06, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Xi Long, San Jose, CA (US);

Hing Yan To, Cupertino, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H05K 1/11 (2006.01); H01L 25/065 (2023.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H05K 1/116 (2013.01); H01L 25/0655 (2013.01); H05K 1/181 (2013.01); H05K 2201/09627 (2013.01);
Abstract

A semiconductor device comprises a printed circuit board (PCB), a plurality of vias, and a communication buss. The PCB comprises a plurality of layers. The first layer of the plurality of layers is configured to receive a first integrated circuit (IC) device and a second IC device. The plurality of vias is disposed within the plurality of layers. A first via of the plurality of vias is configured to be connected to the first IC device, and a second via of the plurality of vias is configured to be connected to the second IC device. The communication bus comprises a first trace connected to the first via. The communication device further comprises a second trace disposed on a third layer of the plurality of layers and connected to the first via. The first trace is disposed on a layer of the plurality of layers other than the second layer.


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