The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jan. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Liang-Shiuan Peng, Taipei, TW;

Chih-Hung Lu, Zhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H10D 1/68 (2025.01); H10D 88/00 (2025.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/76819 (2013.01); H10D 1/696 (2025.01); H10D 88/00 (2025.01); H01L 24/13 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05681 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/401 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01);
Abstract

Some embodiments relate to an integrated chip including a first metal insulator metal (MIM) capacitor disposed over a substrate. The integrated chip further includes a second MIM capacitor disposed over the substrate. The first MIM capacitor has a first outer sidewall facing a second outer sidewall of the second MIM capacitor. A dielectric structure is arranged over and laterally between the first MIM capacitor and the second MIM capacitor. A base conductive layer is arranged between the first MIM capacitor and the second MIM capacitor and has a substantially flat upper surface. A metal core arranged on the substantially flat upper surface of the base conductive layer.


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