The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

May. 27, 2024
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Young Gwang Yoon, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2025.01); H10D 30/60 (2025.01); H10D 64/27 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28097 (2013.01); H01L 21/28088 (2013.01); H10D 30/601 (2025.01); H10D 64/517 (2025.01); H10D 64/667 (2025.01); H10D 64/668 (2025.01); H10D 64/689 (2025.01); H10D 64/691 (2025.01); H10D 84/0137 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.


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