The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Aug. 09, 2023
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Zequn Huang, Hefei, CN;

Kai Sun, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G06F 1/08 (2006.01); G06F 11/10 (2006.01); G11C 11/4076 (2006.01); H03K 5/133 (2014.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/08 (2013.01); G06F 11/106 (2013.01); H03K 5/133 (2013.01); H03K 2005/00058 (2013.01); H03K 2005/00241 (2013.01);
Abstract

Provided in the embodiments of the present disclosure are a delay control circuit and method, and a semiconductor memory. The delay control circuit includes a clock circuit and a delay circuit. The clock circuit is configured to receive a temperature adjustment signal, and generate a first clock signal according to the temperature adjustment signal; and a clock cycle of the first clock signal is a preset value. The delay circuit is configured to receive the first clock signal and an initial command signal, and perform delay processing on the initial command signal according to the first clock signal, so as to obtain a target command signal; and a time interval between the target command signal and the initial command signal meets a preset timing condition.


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