The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Jun. 15, 2022
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/27 (2020.01); G06F 30/392 (2020.01); G06N 3/042 (2023.01); G06N 3/0464 (2023.01); G06N 3/08 (2023.01); G06N 7/00 (2023.01); G06N 20/00 (2019.01); G06V 10/77 (2022.01); G06V 10/82 (2022.01); G06F 119/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06V 10/7715 (2022.01); G06V 10/82 (2022.01); G06F 30/27 (2020.01); G06F 30/392 (2020.01); G06F 2119/06 (2020.01); G06N 3/042 (2023.01); G06N 3/0464 (2023.01); G06N 3/08 (2013.01); G06N 7/00 (2013.01); G06N 20/00 (2019.01);
Abstract
A method, a system, and non-transitory computer readable medium for power and ground (P/G) routing for an integrated circuit (IC) design are provided. The method includes generating input features for a machine-learning (ML) model based on IR drop and routing congestion analysis for a P/G network for the IC design, and modifying a set of P/G vias or a set of P/G wires in the P/G network according to modifications identified by the ML model. The ML model comprises a feature extractor pre-trained using a plurality of images of P/G vias and P/G wires.