The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Aug. 28, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuan-Ting Pan, Taipei, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H01L 21/76224 (2013.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01); H10D 64/693 (2025.01);
Abstract

A semiconductor device includes a substrate, a shallow trench isolation structure, two epitaxial structures, one or more semiconductor channel layers, a gate metal layer and a gate spacer. The shallow trench isolation structure is disposed over the substrate. The epitaxial structures are disposed over the shallow trench isolation structure. The one or more semiconductor channel layers connect the two epitaxial structures. The gate metal layer is located between the epitaxial structures and engages the one or more semiconductor channel layers. The gate spacer is in contact with a sidewall of the gate metal layer. From a cross-section view, a neck portion of the gate metal layer adjacent to and along the one or more semiconductor channel layers, and one side of the neck portion is retracted by a distance relative to the gate spacer, and the distance is greater than 0 and less than or equal to 2 nanometers.


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