The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2025
Filed:
Jun. 26, 2024
Applicant:
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Inventors:
Han-Jong Chia, Hsinchu, TW;
Mauricio Manfrini, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/68 (2025.01); H01L 21/02 (2006.01); H10B 51/30 (2023.01); H10B 53/30 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 1/684 (2025.01); H01L 21/02601 (2013.01); H10B 51/30 (2023.02); H10B 53/30 (2023.02); H10D 1/692 (2025.01); H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/0415 (2025.01); H10D 30/6211 (2025.01); H10D 30/6757 (2025.01); H10D 30/701 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01); H10D 30/62 (2025.01);
Abstract
A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.