The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Jun. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hwail Jin, Seongnam-si, KR;

Ji-Han Ko, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/02118 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/29693 (2013.01); H01L 2224/73 (2013.01); H01L 2224/73103 (2013.01); H01L 2224/73204 (2013.01);
Abstract

A semiconductor package includes a lower semiconductor chip and semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip. Connection bumps are between the lower semiconductor chip and a bottommost one of the semiconductor chips and between the semiconductor chips, A protection layer covers a lateral surface of each of the connection bumps. A mold layer is on the lower semiconductor chip and covering lateral surfaces of the semiconductor chips. The mold layer extends between the bottommost one of the semiconductor chips and the lower semiconductor chip and between the semiconductor chips. The protection layer is between the mold layer and the lateral surface of each of the connection bumps.


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