Semiconductor memory device with multiple banks each including decoding circuit controlled by memory-bank select signals

Abstract

Provided is a semiconductor memory device including a plurality of memory banks. Each of the memory banks includes a first memory cell, a second memory cell, a select circuit, and a decoding circuit. The select circuit is respectively coupled to the first and second memory cells through first and second bit lines, and selects the memory cell to be operated according to a first switch signal and a second switch signal. The decoding circuit generates the first switch signal and the second switch signal according to a memory-bank select signal, a first local column select signal, and a second local column select signal.