The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Jul. 12, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuan-Ting Pan, Taipei, TW;

Kuo-Cheng Chiang, Zhubei, TW;

Shi Ning Ju, Hsinchu, TW;

Yi-Ruei Jihan, Keelung, TW;

Wei Ting Wang, Taipei, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 84/851 (2025.01); H10D 30/6735 (2025.01); H10D 64/017 (2025.01); H10D 84/0177 (2025.01); H10D 84/0179 (2025.01); H10D 84/0188 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/121 (2025.01); H10D 84/0193 (2025.01); H10D 84/85 (2025.01); H10D 84/853 (2025.01);
Abstract

In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.


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