The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Oct. 17, 2022
Applicant:

Imec Vzw, Leuven, BE;

Inventor:

Gaspard Hiblot, Leuven, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 30/67 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/6735 (2025.01); H10D 64/256 (2025.01); H10D 84/0149 (2025.01);
Abstract

A method for forming an interconnection structure for a first transistor and a second transistor is provided. The first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion. The channel portions are stacked above each other on a substrate. The method includes forming a conductive line extending beside and below the second channel portion, forming, on the conductive line, a first vertical interconnect structure for electrically contacting the first channel portion, and thinning the substrate from the backside to expose the conductive line from below. The method further includes forming a via hole exposing the second channel portion from below, filling the via hole with a conductive material to form a second vertical interconnect structure, and forming a conductive structure on the second vertical interconnect structure. A semiconductor device is also provided.


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