The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Dec. 08, 2024
Applicant:

Monolithic 3d Inc., Klamath Falls, OR (US);

Inventors:

Deepak C. Sekar, Sunnyvale, CA (US);

Zvi Or-Bach, Haifa, IL;

Assignee:

Monolithic 3D Inc., Allen, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H01L 21/268 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 41/20 (2023.01); H10B 41/41 (2023.01); H10B 43/20 (2023.01); H10B 61/00 (2023.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 84/03 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 88/00 (2025.01); H10B 41/40 (2023.01); H10B 43/40 (2023.01); H10D 84/80 (2025.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/84 (2023.02); H01L 21/268 (2013.01); H01L 21/6835 (2013.01); H01L 21/76254 (2013.01); H10B 10/00 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 41/20 (2023.02); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H10B 63/845 (2023.02); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 30/711 (2025.01); H10D 84/038 (2025.01); H10D 86/01 (2025.01); H10D 86/011 (2025.01); H10D 86/201 (2025.01); H10D 86/215 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01); H01L 2221/6835 (2013.01); H10B 12/056 (2023.02); H10B 12/36 (2023.02); H10B 41/40 (2023.02); H10B 43/40 (2023.02); H10D 30/6218 (2025.01); H10D 84/80 (2025.01); H10N 70/20 (2023.02); H10N 70/823 (2023.02); H10N 70/8833 (2023.02);
Abstract

A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the first level includes control of power delivery to the at least one third transistor.


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