The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

May. 20, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Chia-En Huang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02);
Abstract

A device includes a word line, a dielectric layer, a gate dielectric layer, a semiconductive layer, a source line, and a memory stack. The word line is over a substrate. The dielectric layer is over the word line and has inner sidewalls over the word line. The gate dielectric layer is in contact with the word line and lines a top surface and inner sidewalls of the dielectric layer. The semiconductive layer is conformally over the gate dielectric layer. The semiconductive layer includes a source portion, a drain portion, and a channel portion. The source portion and the drain portion are over the top surface of the dielectric layer. The channel portion interconnects the source portion and the drain portion and in at a position lower than the source portion. The source line and the memory stack are respectively over the source portion and the drain portion.


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